High Speed: 10 MBd Typical? Low Input Current Capability: 5 mA? Isolated Line Receiver? Computer-Peripheral Interfaces? Microprocessor System Interfaces?
|Published (Last):||26 March 2005|
|PDF File Size:||10.42 Mb|
|ePub File Size:||3.33 Mb|
|Price:||Free* [*Free Regsitration Required]|
High Density Packaging? Low Input Current Capability: 5 mA? High Speed: 10 MBd? The photons are collected in the detector by a photodiode and the current is amplified by a high gain linear amplifier that drives a Schottky clamped open collector output transistor. Each circuit is temperature, current and voltage compensated. The dual channel design minimizes PCB space. They can be used for the digital programming of machine control systems, motors and floating power supplies.
Isolation of High Speed Logic Systems? Microprocessor System Interfaces? Isolated Line Receiver? Computer-Peripheral Interfaces? Ground Loop Elimination? This package occupies approximately one-third the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes.
Note: Use of non-chlorine activated fluxes is highly recommended. See note 1. VF ————? Notes: 1. Bypassing of the power supply line is required with a 0.
F ceramic disc capacitor adjacent to each optocoupler. Total lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 15 mA.
Each channel. Measured between pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. The tPLH propagation delay is measured from the 3. The tPHL propagation delay is measured from the 3. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state i.
CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state i. As illustrated in Figure 15 the VCC and GND traces can be located between the input and the output leads to provide additional noise immunity at the compromise of insulation capability.
Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. High Level Output Current vs. Low Level Output Voltage vs.
Input Diode Forward Characteristic. Output Voltage vs. Forward Input Current. Figure 6. Low Level Output Current vs. Figure 8. Propagation Delay vs.
Pulse Input Current. Pulse Width Distortion vs. Figure Rise and Fall Time vs. Temperature Coefficient of Forward Voltage vs. Input Current. Input Threshold Current vs.
Recommended Printed Circuit Board Layout. Insulation Related Specifications Parameter Min. External Air Gap Clearance Min. External Tracking Path Creepage Min. The propagation delay from low to high tPLH is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high.
Similarly, the propagation delay from high to low tPHL is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low see Figure 7.
PWD can be expressed in percent by dividing the PWD in ns by the minimum pulse width in ns being transmitted. Propagation delay skew, tPSK, is an important parameter to consider in parallel data appli- cations where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times.
If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given H group of optocouplers which are operating under the same conditions i.
As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 18 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers.
The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler.
Figure 18 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK.
A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The tPSK specified optocouplers offers the advantages of guaranteed specifications for propagation delays, pulse-width distortion and propagation delay skew over the recommended temperature, input current, and power supply ranges.
Parallel Data Transmission Example. For more information call: United States: call your local HP sales office listed in your telephone directory. Ask for a Components representative.
HCPL0631 Fairchild Optoelectronics Group
HCPL-0631 Avago Technologies US Inc., HCPL-0631 Datasheet