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Five Hermetically Sealed Package Configurations? High Radiation Immunity? Reliability Data? TTL Circuit Compatibility? Quad channel devices are available by special order in the 16 pin DIP through hole packages. Military and Space?
High Reliability Systems? The output of the detector is an open collector Schottky clamped transistor. Package styles for these parts are 8 and 16 pin DIP through hole case outlines P and E respectively , and 16 pin surface mount DIP flat pack case outline F , leadless ceramic chip carrier case outline 2. Devices may be purchased with a variety of lead bend and plating options. See Selection Guide Table for details. Because the same electrical die emitters and detectors are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifications, and performance characteristics shown in the figures are identical for all parts.
Occasional exceptions exist due to package variations and limitations, and are as noted. Additionally, the same package assembly processes and materials are used in all devices. Single channel DIP has an enable pin 7. This option is available on commercial and hi-rel product in 8 and 16 pin DIP see drawings below for details. This option is available on commercial and hi-rel product in 8 and 16 pin DIP.
DSCC Drawing part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered with solder dipped terminals as a standard feature.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option has solder dipped leads. An external 0. F bypass capacitor must be connected between VCC and ground for each package type. VCC 0. Units Fig. Each channel. All devices are considered two-terminal devices; I I-O is measured between all input leads or terminals shorted together and all output leads or terminals shorted together. Measured between each input pair shorted together and all output connections for that channel shorted together.
Measured between adjacent input pairs shorted together for each multichannel device. Use the single channel parameter limits for each channel. This is a momentary withstand test, not an operating condition. It is essential that a bypass capacitor 0. F, ceramic be connected from VCC to ground. Total lead length between both ends of this external capacitor and the isolator connections should not exceed 20 mm. No external pull up is required for a high logic state on the enable input.
The tELH enable propagation delay is measured from the 1. The tEHL enable propagation delay is measured from the 1. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified for all lots not specifically tested. Figure 1. High Level Output Current vs. Figure 2. Input-Output Characteristics. Figure 3. Input Diode Forward Characteristic. Figure 5. Figure 4. Figure 6. Propagation Delay vs. Figure 7.
Figure 9. Enable Propagation Delay vs. Figure 8. Figure COM Copyright? Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www. Free Download.
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HCPL 5631 PDF
HCPL-5631 - Avago Technologies - Semiconductors