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They are specifically designed for Off? Line and DC? DC converter applications offering the designer a cost? These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET.

Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle? These devices are available in an 8? The SOIC? Trimmed Oscillator for Precise Frequency Control? Oscillator Frequency Guaranteed at kHz? Current Mode Operation to kHz? Automatic Feed Forward Compensation? Latching PWM for Cycle? Cycle Current Limiting? Internally Trimmed Reference with Undervoltage Lockout?

High Current Totem Pole Output? Undervoltage Lockout with Hysteresis? Low Startup and Operating Current? Figure 1. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and change control. DC min? Reference Load Regulation 2. Pin 14? Pin Function Description 1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation. It is normally connected to the switching power Feedback supply output through a resistor divider.

The PWM uses this information to terminate the output switch conduction. Operation to kHz is possible. This pin is the combined control circuitry and power ground. Peak currents up to 1. This is the reference output. It provides charging current for capacitor CT through resistor RT. This pin is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry.

With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. These pins are not internally connected. A representative block diagram is shown in Figure Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 5. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high.

This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. These internal circuit refinements minimize variations of oscillator frequency and maximum output duty cycle. The results are shown in Figures 4 and 5.

In many noise? This can be accomplished by applying a clock signal to the circuit shown in Figure For reliable locking, the free? A method for multi? By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved.

Error Amplifier A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical DC voltage gain of 90 dB, and a unity gain bandwidth of 1.

The non? The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is? This guarantees that no drive pulses appear at the Output Pin 6 when pin 1 is at its lowest state VOL. This occurs when the power supply is operating and the load is removed, or at the beginning of a soft?

Thus the error signal controls the peak inductor current on a cycle? The inductor current is converted to a voltage by inserting the ground? Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1. A simple method to adjust this voltage is shown in Figure The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature.

Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk max clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time.

The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability refer to Figure The positive power supply terminal VCC and the reference output Vref are each monitored by separate comparators. Each has built? The Vref comparator upper and lower thresholds are 3.

The large hysteresis and low startup current of the UCXB makes it ideally suited in off? DC converter applications. Its purpose is to protect the IC from excessive voltage that can occur during system startup. These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active.

This characteristic eliminates the need for an external pull? Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry.

This becomes particularly useful when reducing the Ipk max clamp level. The separate VC supply input allows the designer added flexibility in tailoring the drive voltage independent of VCC.

Figure 26 shows proper power and control ground connections in a current? Reference The 5. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short? Design Considerations Do not attempt to construct the converter on wire? High frequency circuit layout techniques are imperative to prevent pulse? This is usually caused by excessive noise pick?

Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low?

Ceramic bypass capacitors 0. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI.

The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise? Figure 20A shows the phenomenon graphically. At t0, switch conduction begins, causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t1, the Current Sense Input reaches the threshold established by the control voltage.

This causes the switch to turn off and the current to decay at a slope of m2, until the next oscillator cycle. The unstable condition can be shown if a perturbation is added to the control voltage, resulting in a small DI dashed line.

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